View CD54ACT623F3A_130734.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

SEMICONDUCTOR
CD54ACT623F3A
Octal Bus Transceiver Three-State, Non-Inverting
Description
The CD54ACT623F3A is an octal bus transceiver that utilizes Harris Advanced CMOS Logic technology. It is a noninverting three-state bidirectional transceiver-buffer that allows for two-way transmission from "A" bus to "B" bus or "B" bus to "A" bus depending on the logic levels of the Output Enable (OEAB, OEBA) inputs. The dual Output Enable provision gives these devices the capability to store data by simultaneously enabling OEAB and OEBA. Each output reinforces its input under these conditions, and when all other data sources to the bus lines are at high-impedance, both sets of bus lines will remain in their last states.
July 1998
Features
* This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. * Exceeds 2kV ESD Protection MIL-STD-883, Method 3015 * Meets JEDEC Standard No. 20 * SCR - Latch-Up-Resistant CMOS Process and Circuit Design * Speed of Bipolar FAST/A/S with Significantly Reduced Power Consumption * Functionally and Pin-Compatible with Industry 54 Bipolar Types in the FAST, AS and S Series * Balanced Propagation Delays * Military Operating Temperature Range - Ceramic (CERDIP) 54 Series: . . . . . . . . -55 to 125oC * 24mA Output Drive Current, Drives 75 Lines without Need for Terminations * Fan Out (Over Temperature) - ACL Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2400 - FAST Loads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 - AS Loads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 * Operation Voltage . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
Ordering Information
PART NUMBER CD54ACT623F3A NOTE: 1. Wafer and die for this part number is available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information. TEMP. RANGE (oC) -55 to 125 PACKAGE 20 Ld CERDIP PKG. NO. F20.3
Pinout
OEAB A0 A1 1 2 3 4 5 6 7 8 9 20 VCC 19 OEBA 18 B0 17 B1 16 B2 15 B3 14 B4 13 B5 12 B6 11 B7
Functional Diagram
A0 A1 A2 A3 A4 A5 A6 A7 2 3 4 5 6 7 8 9 1 OEAB OEBA 19 18 17 16 15 14 13 12 11 B0 B1 B2 B3 B4 B5 B6 B7
A2 A3 A4 A5 A6 A7
GND 10
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
(c) Harris Corporation 1998
File Number
3917.1
1
CD54ACT623F3A
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .50mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .50mA DC VCC or Ground Current, ICC or IGND (Note 2) . . . . . . . . .100mA
Thermal Information
Thermal Resistance (Typical, Note 4) JA (oC/W) JC (oC/W) CERDIP Package . . . . . . . . . . . . . . . . 80 22 Maximum Junction Temperature (Hermetic Package or Die) . . . 175oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC (Note 3) . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 2. For up to 4 outputs per device, add 25mA for each additional output. 3. Unless otherwise specified, all voltages are referenced to ground. 4. JA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
TEST CONDITIONS PARAMETER High Level Input Voltage Low Level Input Voltage High Level Output Voltage SYMBOL VIH VIL VOH VI (V) VIH or VIL IO (mA) -0.05 -24 -50 (Note 6, 7) Low Level Output Voltage VOL VIH or VIL 0.05 24 50 (Note 6, 7) Input Leakage Current Three-State or Leakage Current Quiescent Device Current Additional Supply Current per Input Pin TTL Inputs High 1 Unit Load NOTES: 5. Tested 100%. 6. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize power dissipation. 7. Test verifies a minimum transmission-line-drive capability of 75 for 54ACT Series. II IOZ VCC or GND VIH or VIL VO = VCC or GND VCC or GND VCC -2.1 VCC (V) 4.5 to 5.5 4.5 to 5.5 4.5 4.5 5.5 4.5 4.5 5.5 5.5 5.5 25oC MIN 2 (Note 5) 4.4 3.94 (Note 5) MAX 0.8 (Note 5) 0.1 0.36 (Note 5) 0.1 (Note 5) 0.5 (Note 5) 8 (Note 5) 2.4 -55oC TO 125oC MIN 2 (Note 5) 4.4 3.7 (Note 5) 3.85 MAX 0.8 (Note 5) 0.1 0.5 (Note 5) 1.65 1 (Note 5) 10 (Note 5) 160 (Note 5) 3 UNITS V V V V V V V V A A
ICC ICC
0 -
5.5 4.5 to 5.5
-
-
A mA
2
CD54ACT623F3A
ACT Input Load Table
INPUT An, Bn OEBA OEAB UNIT LOAD 0.83 0.64 0.15
NOTE: Unit load is ICC limit specified in DC Electrical Specifications Table, e.g., 2.4mA max at 25oC.
Switching Specifications Input tr, tf = 3ns, CL = 50pF (Worst Case)
-55oC TO 125oC PARAMETER Propagation Delay, Data to Output Propagation Delay, Output Disable to Output Propagation Delay, Output Enable to Output Minimum (Valley) VOH During Switching of Other Outputs (Output Under Test Not Switching) Maximum (Peak) VOL During Switching of Other Outputs (Output Under Test Not Switching) Three-State Output Capacitance Input Capacitance Power Dissipation Capacitance NOTES: 8. Limits tested 100%. 9. 3.3V Min = 3.6V, Max = 3V. 10. 5V Min = 5.5V, Max = 4.5V 11. CPD is used to determine the dynamic power consumption per gate. PD = VCC2 fi (CPD + CL) + VCC ICC where fi = input frequency, CL = output load capacitance, VCC = supply voltage. SYMBOL tPLH, tPHL tPLZ, tPHZ tPZL, tPZH VOHV See Figure 1 VOLP See Figure 1 CO CI CPD (Note 11) VCC (V) 5 (Note 10) 5 5 5 5 MIN 1.8 2.5 2.5 TYP 4 at 25oC 1 at 25oC 79 MAX 10.6 (Note 8 14.4 (Note 8) 14.4 (Note 8) 15 10 UNITS ns ns ns V V pF pF pF
Burn-In Test Circuit Connections (Use DC II for F3A Burn-In and AC for Life Test)
DC BURN-IN I DC CD54ACT623 OPEN 2-9 GROUND 1, 10-19 VCC (6V) 20 OPEN 11-18 DC BURN-IN II GROUND 10 VCC (6V) 1-9, 19, 20 OSCILLATOR AC CD54ACT623 OPEN GROUND 10 1/2 VCC (3V) 11-18 VCC (6V) 19, 20 50kHz 2-9 25kHz 1
NOTE: Each pin except VCC and Gnd will have a resistor of 2k-47k.
OUTPUT RL 500 DUT OUTPUT LOAD CL 50pF
CD54ACT Input Level Input Switching Voltage, VS Output Switching Voltage, VS 3V 1.5V 0.5 VCC
FIGURE 1. PROPAGATION DELAY TIMES
3

▲Up To Search▲

Price & Availability of CD54ACT623F3A

	To Download CD54ACT623F3A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .